The PDP-11 processor requires a particular power up/power down sequence in order to properly startup and shutdown. The BDCOK H signal is supposed to be activated 3ms, or more, after the voltages reach their normal levels, then BPOK H is supposed to go active 70ms, or more after BDCOK H in order for the processor to initialize. The system also needs a power switch, a enable/halt switch and a line-time clock (LTC) enable/disable switch in order to properly function. Power, Run and LTC LEDs are also nice to have, for troubleshooting purposes. Therefore, a fair amount of additional support circuitry is required for normal system use.
I started out by using the PDP-11/03 front panel schematic, from the H780 power supply maintenance print set, as my basis of design. DEC's actual design requires parts that are now obsolete, but their theory was still useful. The halt and LTC switches require debounce circuits and open collector bus drivers. The Run and LTC LEDs require one-shot circuits, because these signals are not constantly on when running. The one shot provides a pulse that spans the longest period that the signal would be low, but will still eventually drop out, when the signal stays low for too long. The power switch and LED do not need this sort of conditioning.
My front panel board does not cycle BPOK H, and instead activates it whenever AC power is applied to the power supply. The power supply activates PS_OK around 100-500ms after the voltages normalize, and this signal is currently used to activate BDCOK H. This only works if the processor has its own wake-up sequencing, however. Otherwise, the processor comes up halted at some random address, or does not come up. My next step is to come up with a proper sequencing circuit to fix this.
A loaded Q-bus needs open collector signals, with around 70 mA of drive current from each signal, which is extremely high by todays standards. Most parts that were capable of meeting this requirement are now obsolete. To meet this requirement, I used PN2222A switching transistors as bus drivers. The PN2222A can drive up to an amp of current, which is more than enough. These transistors are not quite as fast as TTL logic, but the signals being driven are from the toggle switches and the power supply, so speed is not a factor.
Since I have a naked backplane and card cage, I decided to mount the front panel board to the right side of the card cage on a set of nylon stand-offs, leveraging the existing mounting holes in the card frame. The switches would be right-angle models mounted at the front of the board, for easy access. The bus and power supply connections would be at the back.
After designing the new board, I decided to not breadboard the circuits, and just went ahead and sent the design to the good folks at OSH Park for fabrication. This small lack of due diligence would come back to bite me later.
Here are the boards after I received them.
One of the boards after cleanup and assembly.
After installation.
Complete system, with the power supply and boards.
I had to make 3 field modifications to the board to correct some issues I had with driving the LEDs and the BDCOK H line. My latest "Revision B" design is essentially this board after these modifications. The schematic and gerber files are located at the bottom of this page. I have not had this board fabricated, and cannot verify its operation. You are welcome to use these files at your own risk.
One feature I want to add is an initialize, or reset, switch. By cycling the BDCOK H signal (but not the power supply), the processor will re-initialize itself. The dynamic memory will also likely lose its contents in the process. The reason for this feature is to have the system reboot on its own, rather than halting it and entering 173000G at the ODT to reboot it.