Module Comparisons Third-Party Products Functional Information

Q-bus Signals

Bus Pin Signal Mnemoic Signal Name Signal Function
AA1 BSPARE1
BIRQ5 L
Bus Spare 1
Interrupt Request 5
Not assigned in systems with an LSI-11 (M7264) processor.
Terminated in systems with an LSI-11/2 (M7270) processor.
Interrupt Request priority level 5 in systems with an F11 or J11 processor.
AB1 BSPARE2
BIRQ6 L
Bus Spare 2
Interrupt Request 6
Not assigned in systems with an LSI-11 (M7264) processor.
Terminated in systems with an LSI-11/2 (M7270) processor.
Interrupt Request priority level 6 in systems with an F11 or J11 processor.
AC1 BSPARE3
BDAL16 L
Bus Spare 3
Address 16/Parity Line
Not assigned in systems with an LSI-11 (M7264) processor.
Terminated in systems with an LSI-11/2 (M7270) processor.
In systems with an F11 or J11 processor, address line 16 during addressing protocol; parity control line during data transfer protocol.
AD1 BSPARE4
BDAL17 L
Bus Spare 4
Address 17/Parity Line
Not assigned in systems with an LSI-11 (M7264) processor.
Terminated in systems with an LSI-11/2 (M7270) processor.
In systems with an F11 or J11 processor, address line 17 during addressing protocol; parity control line during data transfer protocol.
AE1 SSPARE1
STOP L
+5B
Special Spare LSI-11/2 (M7270) processors generate a 380 ns clock output (STOP L) on this pin, which can be used for extending the bus timeout delay.
Not assigned or bussed otherwise in Digital cable or backplane assemblies; available for user interconnection.
Optionally, this pin may be used for +5 V battery (+5B) backup power to keep critical circuits alivve during power failures. A jumper is required on LSI-11 Bus options to open (disconnect) the +5B circuit in systems that use this line as SSPARE1.
AF1 SSPARE2
SRUN
Special Spare Not assigned or bussed in Digital cable or backplane assemblies; available for user interconnection. In the highest priority device slot, the processor may use this pin for a signal to indicate its RUN state.
AH1 SSPARE3
SRUN
Special Spare Not assigned or bussed in Digital cable or backplane assemblies; available for user interconnection. In the highest priority device slot, the processor may use this pin for a signal to indicate its RUN state.
AJ1 GND Ground System signal and DC return.
AK1
AL1
MSPAREA
MSPAREA
Maintenance Spares Normally connected together on the backplane at each option location (not a slot-to-slot bussed connection).
LSI-11/2 (M7270) processors use AK1 as a bus timeout enable (MTOE L) and then ground AL1 internally, allowing the logic to function normally. Cutting the connection between these two pins and inserting external logic will allow the bus timeout to be extended.
AM1 GND Ground System signal and DC return.
AN1 BDMR L DMA Request Device asserts this signal to request bus mastership.
AP1 BHALT L Processor Halt When signal is asserted, the processor responds by going into its halt state (generally console ODT mode.)
AR1 BREF L Memory Refresh Terminated by processor modules, with no refresh.
Otherwise, used during refresh protocol to override memory bank selection decoding and cause all banks to be selected.
Asserted or negated with BRPLY L by Block Mode Slave Devices to indicate to the Bus Master if the slave can accept another Block Mode DIN or DOUT transfer.
AS1 +5B
+12B
Battery +12 or +5 VDC battery backup power to keep critical circuits alive during power failures. This signal is not bussed to BS1 in all Digital backplanes. A jumper is required on all LSI-11 Bus options to open (disconnect) the backup circuit from the bus in systems that use this line at the alternate voltage.
AT1 GND Ground System signal and DC return.
AU1 PSPARE1 Power Spare 1 Not assigned a function; not recommended for use. If a backplane is bussing -12 V (on pin BB2) and a module is accidentially inserted upside down in the backplane, -12 VDC appears on pin AU1. If AU1 is unused on this module, no damage will occur.
AV1 +5B +5 V Battery Backup Power To keep critical circuits alive during power failures.
BA1 BDCOK H DC Power OK Power supply generated signal that is asserted when there is sifficient DC voltage available to sustain reliable system operation. Part of Power Up and Power Down protocol and Boot protocol.
BB1 BPOK H AC Power OK Asserted by the power supply when primary power is normal. When negated during processor operation, a power failure sequence is initiated. Part of Power Up and Power Down protocol and Boot protocol.
BC1 SSPARE4
BDAL18 L
Special Spare 4
Address Line 18
Special spare in older (pre Q22-bus) LSI-11 Bus systems.
Not assigned or bussed in non-Q22-bus cable and backplane assemblies.
Bussed in Q22-bus backplane and cable assemblies.
BD1 SSPARE5
BDAL19 L
Special Spare 5
Address Line 19
Special spare in older (pre Q22-bus) LSI-11 Bus systems. Not assigned or bussed in non-Q22-bus cable and backplane assemblies.
Bussed in Q22-bus backplane and cable assemblies.
BE1 SSPARE6
BDAL20 L
Special Spare 6
Address Line 20
Special spare in older (pre Q22-bus) LSI-11 Bus systems. Not assigned or bussed in non-Q22-bus cable and backplane assemblies.
Bussed in Q22-bus backplane and cable assemblies.
BF1 SSPARE7
BDAL21 L
Special Spare 7
Address Line 21
Special spare in older (pre Q22-bus) LSI-11 Bus systems. Not assigned or bussed in non-Q22-bus cable and backplane assemblies.
Bussed in Q22-bus backplane and cable assemblies.
BH1 SSPARE8 Special Spare 8 Not assigned or bussed in Digital cable or backplane assemblies; available for user interconnection.
BJ1 GND Ground System signal and DC return.
BK1
BL1
MSPAREB
MSPAREB
Maintenance Spares Normally connected together on the backplane at each option location (not a slot-to-slot bussed connection).
BM1 GND Ground System signal and DC return.
BN1 BSACK L DMA Acknowledge This signal is asserted by a DMA device in response to the processor's BDMGO L signal, indicating that the DMA device is accepting bus mastership. Device remains bus master until it negates BSACK L.
BP1 BIRQ7 L Interrupt Request 7 Interrupt request priority level 7.
BR1 BEVNT L External Event Interrupt Request The processor latches the leading edge and arbitrates as an interrupt. A typical use of this signal is a line time clock interrupt.
BS1 +12B +12V Battery +12 VDC battery backup power (not bussed to AS1 in all Digital backplanes.
BT1 GND Ground System signal and DC return.
BU1 PSPARE2 Power Spare 2 Not assigned a function, not recommended for use. If a backplane is bussing -12 V (on pin AB2) and a module is accidentially inserted upside down in the backplane, -12 VDC appears on pin BU1. If BU1 is unused on this module, no damage will occur.
BV1 +5 +5 V Power Normal +5 VDC System power
AA2 +5 +5 V Power Normal +5 VDC System power
AB2 -12 -12 V Power -12 VDC (optional) power for devices requiring this voltage.
AC2 GND Ground System signal and DC return.
AD2 +12 +12 V Power Normal +12 VDC system power.
AE2 BDOUT L Data Output BDOUT, when asserted, implies that valid data is available on BDAL <15:0> L and that an output transfer, with respect to the bus master device, is taking place. BDOUT L is de-skewed with respect to the data on the bus.
AF2 BRPLY L Reply BRPLY L is asserted in response to BDIN L or BDOUT L and during IAK transaction. It is generated by a slave device to indicate that it will place its data on the BDAL bus or that it will accept data from the bus, according to the appropriate protocol.
AH2 BDIN L Data Input BDIN L is used for two types of bus operation:
  1. When asserted during BSYNC L time, BDIN L implies an input transfer with respect to the current bus master and requires a response (BRPLY L) from the addressed slave.
  2. The interrupt fielding processor initiates interrupt service by asserting TDIN L followed by TIACK L.
AJ2 BSYNC L Synchornize BSYNC L is asserted by the bus master device to indicate that it has placed an address on the bus. The transfer is in process until BSYNC L is negated. In block mode BSYNC L remains asserted until the last transfer cycle is completed.
AK2 BWTST L Write/Byte BWTBT L is used in two ways to control a bus cycle:
  1. It is asserted during the address portion of a cycle to indicate that an output cycle is to follow (DATO, DATOB DATBO) rather than an input cycle.
  2. It is asserted during the Data portion of DATAOB or DATAIOB bus cycle, to indicate a byte rather than a word transfer is to take place.
AL2 BIRQ4 L Interrupt Request 4 Interrupt Request priority level 4.
AM2
AN2
BIAKI L
BIAKO L
Interrupt Acknowledge In
Interrupt Acknowledge Out
In accordance with interrupt protocol, the processor asserts BIAKO L to acknowledge an interrupt. The bus transmits this to BIAKI L of the next priority device (electrically closest to the processor). This device accepts the Interrupt Acknowledge under two conditions:
  1. The device requested the bus by asserting an interrupt, BIRQX L.
  2. The device had the highest priority interrupt request on the bus at the time of the preceeding BDIN L assertion.
If both of these conditions are not met, the device asserts BIAKO L to the next device on the bus. This process continues in a daisy-chain fashion until the device with the highest interrupt priority receives the Interrupt Acknowledge (IAK) signal and proceeds with Interrupt Protocol.
AP2 BBS7 Bank 7 Select When the Bus Master asserts TADDR, it asserts this signal to reference the I/O page (including that portion of the I/O page reserved for nonexistent memory). The address on BDAL <12:0> L when BBS7 L is asserted is the address within the I/O page. During DATBI Transfers, the Bus Master asserts this signal with the first data transfer until the last transfer to indicate to the Block Mode slave that there will be subsequent transfers.
AR2
AS2
BDMGI L
BDMGO L
DMA Grant In
DMA Grant Out
The bus arbitrator asserts this signal to grant bus mastership to a requesting device, according to the bus mastership protocol. The signal is passed in a daisy-chain from the arbitrator (as BDMGO L) through the bus to BDGMI L of the next priority device (electrically closest device on the bus). This device accepts the grant only if it requested to be bus master (by assertion BDMA L). If not, the device passes the grant (asserts BDMGO L) to the next device on the bus. This process continues until the requesting device acknowledges the grant by asserting BSACK L after BRPLY L and BSYNC L are both negated.
AT2 BINIT L Initialize This signal is used for system reset. All devices on the bus are to return to a known, initial state; i.e., registers are reset to zero, all Bus drivers are disabled and logic is reset to state 0, ready to be addressed for operations. Exceptions should be completely documented in programming and engineering specifications for the device.
AU2 BDAL0 L Data/Address Line 00 Specifies high or low byte during address for DATOB and DATIOB cycles.
AV2 BDAL1 L Data/Address Line 01 Data/address line 01.
BA2 +5 +5 V Power +5 VDC power.
BB2 -12 -12 VDC Power Optional, not required for DIGITAL LSI-11 or F11 hardware options.
BC2 GND Ground System signal and DC return.
BD2 +12 +12 VDC Power +12 VDC power.
BE2 BDAL2 L Data/Address Line 02 Data/address line 02.
BF2 BDAL3 L Data/Address Line 03 Data/address line 03.
BH2 BDAL4 L Data/Address Line 04 Data/address line 04.
BJ2 BDAL5 L Data/Address Line 05 Data/address line 05.
BK2 BDAL6 L Data/Address Line 06 Data/address line 06.
BL2 BDAL7 L Data/Address Line 07 Data/address line 07.
BM2 BDAL8 L Data/Address Line 08 Data/address line 08.
BN2 BDAL9 L Data/Address Line 09 Data/address line 09.
BP2 BDAL10 L Data/Address Line 10 Data/address line 10.
BR2 BDAL11 L Data/Address Line 11 Data/address line 11.
BS2 BDAL12 L Data/Address Line 12 Data/address line 12.
BT2 BDAL13 L Data/Address Line 13 Data/address line 13.
BU2 BDAL14 L Data/Address Line 14 Data/address line 14.
BV2 BDAL15 L Data/Address Line 15 Data/address line 15.

References


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